(1) Field of the Invention
The present invention relates to a testing device and a testing method for a semiconductor integrated circuit (e.g., a LCD driver IC, etc.) that incorporates a multiple number of D/A converters and outputs voltages from the D/A converters via the associated output terminals as well as a storage medium having the testing program stored therein. In particular, the present invention relates to a testing device, a testing method and a storage medium having the testing program stored therein, which enable very quick and highly precise test of the output voltages from the D/A converters.
(2) Description of the Prior Art
With the development of LCD panels into a high precision configuration, LCD driver LSIs incorporated in LCD panels have become developed to handle a greater number of outputs and a greater number of tones. For such tonal display, each output circuit in the LCD driver LSI incorporates an individual D/A converter to output a tonal voltage. For example, a 6 bit D/A converter can display 64 levels of tones while a 8 bit D/A converter can display 256 levels of tones.
Upon the test for such a LCD driver LSI, it is checked if all the tonal voltage levels output from individual D/A converters fall within respective correct (pass) ranges, as shown in FIG. 1.
FIG. 2 is a conceptual view illustrating a conventional testing method by using a test example of a LCD driver LSI 51 incorporating xe2x80x98mxe2x80x99 outputs.
A semiconductor testing device (tester) 52 is used to supply an input signal to LCD driver LSI 51 so that each incorporated D/A converter (not shown) outputs a voltage level corresponding to the first tonal level. The voltage levels corresponding to the first tonal level are output from associated output terminals (output 1, . . . , output m) of LCD driver LSI 51 and supplied to input terminals (V) of tester 52. In tester 52, matrix switches (not shown) are sequentially turned on and off so that the output voltages corresponding to the first tonal level are sequentially measured from the first output to the m-th output, one by one, using a high accuracy analog voltage measuring device (not shown) incorporated in the tester. The measured results are sequentially stored in an incorporated data memory (not shown). This process is repeated by the number of tonal levels until all pieces of data (m outputs) for all tonal levels (n levels) are stored into the memory. As a result, mxc3x97n pieces of data will be stored into the memory. The data stored in this memory is subjected to a series of logical and arithmetical operations through an unillustrated processing unit incorporated in tester 52 so as to check each tonal voltage of each output.
In such a test of a LCD driver LSI 51, with the development towards a greater number of outputs and a greater number of tones, the amount of data to be picked up and the time required for data processing have increase, so that the testing time increases sharply. Further, increase of the tonal levels in number will make the potential difference between adjacent tonal voltage levels smaller, requiring a greater precision for measuring the voltages of all the tonal levels, which results in a further longer time for testing.
Since, with the thus development towards a greater number of outputs and a greater number of tones, the conventional testing method should handle an increased amount of data and perform very high-accurate voltage measurements for all the tonal output voltages, the testing time has become markedly longer and the test cost has increased sharply.
The present invention has been completed in view of the above prior art situation, and it is therefore an object of the present invention to provide a testing device, a testing method and a storage medium having the testing program stored therein, which enable very quick and highly precise test of semiconductor integrated circuits.
In order to achieve the above object, the present invention is configured as follows:
In accordance with the first aspect of the present invention, a testing device for a semiconductor integrated circuit which incorporates a multiple number of D/A converters and outputs voltages from the D/A converters via associated output terminals, includes:
a voltage measuring means for measuring the special output voltage corresponding to each tonal level output from a special output terminal of a special D/A converter and computing the difference between the special output voltage and the associated expected voltage as a special differential voltage;
differential amplifying means which, for each tone, receives the special output voltage and output voltages from the output terminals other than the special output terminal and calculates differential voltages and outputs the amplified differential voltages; and
a comparing and determining means for determining whether the amplified differential voltages output from the differential amplifying means fall within a determination voltage range which is specified in accordance with the special differential voltage dependent on each tone.
In accordance with the second aspect of the present invention, the testing device for a semiconductor integrated circuit, having the above first feature is characterized in that the number of differential amplifying means is equal to the number of the output terminals other than the special output terminal, each of the differential amplifying means has an input for receiving a corresponding output voltage output from one of the output terminals other than the special output terminal and another input for receiving the special output voltage in common, and the comparing and determining means effects simultaneous judgement as to all the amplified differential voltages output from the differential amplifying means.
In accordance with the third aspect of the present invention, the testing device for a semiconductor integrated circuit, having the above first or second feature is characterized in that the upper and lower limit voltage values that specify the determination voltage range is set up by shifting the standard upper and lower limit voltage values which are given previously in conformity with the expected voltage value by a fixed value that corresponds to the special differential voltage value.
In accordance with the fourth aspect of the present invention, a testing method for a semiconductor integrated circuit which incorporates a multiple number of D/A converters and outputs voltages from the D/A converters via associated output terminals, includes the steps of:
measuring the special output voltage corresponding to each tonal level output from a special output terminal of a special D/A converter and computing the difference between the special output voltage and the associated expected voltage as a special differential voltage;
for each tone, receiving the special output voltage and output voltages from the output terminals other than the special output terminal, calculating differential voltages and outputting the amplified differential voltages; and
determining whether the amplified differential voltages output from the differential amplifying means fall within a determination voltage range which is specified in accordance with the special differential voltage dependent on each tone.
In accordance with the fifth aspect of the present invention, a testing method for a semiconductor integrated circuit which incorporates a multiple number of D/A converters and outputs voltages from the D/A converters via associated output terminals, includes the steps of:
measuring the special output voltage corresponding to each tonal level output from a special output terminal of a special D/A converter and computing the difference between the special output voltage and the associated expected voltage as a special differential voltage;
for each tone, receiving the special output voltage and output voltages from the output terminals other than the special output terminal, calculating differential voltages and outputting the amplified differential voltages; and
for determining whether the amplified differential voltages output from the differential amplifying means fall within a determination voltage range which is specified in accordance with the special differential voltage dependent on each tone, receiving the amplified differential voltages corresponding to associated output terminals in parallel and effecting simultaneous judgement as to whether all the amplified differential voltages fall within the determination voltage range.
In accordance with the sixth aspect of the present invention, the testing method for a semiconductor integrated circuit, having the above fourth or fifth feature, is characterized in that the upper and lower limit voltage values that specify the determination voltage range are set up by shifting the standard upper and lower limit voltage values which are given previously in conformity with the expected voltage value by a fixed value that corresponds to the special differential voltage value.
In accordance with the seventh aspect of the present invention, the testing method for a semiconductor integrated circuit, having the above sixth feature, further includes the steps of:
determining whether the special output voltage falls within the standard voltage range specified by the upper and lower standard voltage values;
regarding the semiconductor integrated circuit as a defective when the special output voltage falls out of the standard voltage range; and
regarding the semiconductor integrated circuit as a non-defective if the amplified deferential voltages fall within the determination voltage range while regarding the semiconductor integrated circuit as a defective if any of the amplified deferential voltages falls out of the determination voltage range, in the case where the special differential voltage falls within the standard voltage range.
In accordance with the eighth aspect of the present invention, the testing method for a semiconductor integrated circuit, having the above fourth feature is characterized in that, even when the upper and lower limit values of the determination voltage range varies as the tonal level output from the terminals of the semiconductor integrated circuit is switched from one to another, the width of the determination voltage range is constant.
In accordance with the ninth aspect of the present invention, the testing method for a semiconductor integrated circuit, having the above fifth feature is characterized in that, even when the upper and lower limit values of the determination voltage range varies as the tonal level output from the terminals of the semiconductor integrated circuit is switched from one to another, the width of the determination voltage range is constant.
In accordance with the tenth aspect of the present invention, the testing method for a semiconductor integrated circuit, having the above sixth feature is characterized in that, even when the upper and lower limit values of the determination voltage range varies as the tonal level output from the terminals of the semiconductor integrated circuit is switched from one to another, the width of the determination voltage range is constant.
In accordance with the eleventh aspect of the present invention, the testing method for a semiconductor integrated circuit, having the above seventh feature is characterized in that, even when the upper and lower limit values of the determination voltage range varies as the tonal level output from the terminals of the semiconductor integrated circuit is switched from one to another, the width of the determination voltage range is constant.
In accordance with the twelfth aspect of the present invention, the testing method for a semiconductor integrated circuit, having the above seventh feature is characterized in that the width of the determination voltage range is narrowed stepwise until the device under test is determined as a defective.
In accordance with the thirteenth aspect of the present invention, the testing method for a semiconductor integrated circuit, having the above twelfth feature is characterized in that semiconductor integrated circuits under test are classified into ranks, based on the variations of the output voltages in the determination voltage range when each device under test was determined as a defective.
The fourteenth aspect of the present invention resides in a storage medium having a testing program stored therein for testing a semiconductor integrated circuit, which enables execution of a testing method for a semiconductor integrated circuit which incorporates a multiple number of D/A converters and outputs voltages from the D/A converters via associated output terminals, comprising the steps of:
measuring the special output voltage corresponding to each tonal level output from a special output terminal of a special D/A converter and computing the difference between the special output voltage and the associated expected voltage as a special differential voltage;
for each tone, receiving the special output voltage and output voltages from the output terminals other than the special output terminal, calculating differential voltages and outputting the amplified differential voltages; and
determining whether the amplified differential voltages output from the differential amplifying means fall within a determination voltage range which is specified in accordance with the special differential voltage dependent on each tone.
The fifteenth aspect of the present invention resides in a storage medium having a testing program stored therein for testing a semiconductor integrated circuit, which enables execution of a testing method for a semiconductor integrated circuit which incorporates a multiple number of D/A converters and outputs voltages from the D/A converters via associated output terminals, comprising the steps of:
measuring the special output voltage corresponding to each tonal level output from a special output terminal of a special D/A converter and computing the difference between the special output voltage and the associated expected voltage as a special differential voltage;
for each tone, receiving the special output voltage and output voltages from the output terminals other than the special output terminal, calculating differential voltages and outputting the amplified differential voltages; and
for determining whether the amplified differential voltages output from the differential amplifying means fall within a determination voltage range which is specified in accordance with the special differential voltage dependent on each tone, receiving the amplified differential voltages corresponding to associated output terminals in parallel and effecting simultaneous judgement as to whether all the amplified differential voltages fall within the determination voltage range.
The sixteenth aspect of the present invention resides in the storage medium having the fourteenth or fifteenth feature for having a testing program stored therein for testing a semiconductor integrated circuit, which enables execution of a testing method wherein the upper and lower limit voltage values that specify the determination voltage range are set up by shifting the standard upper and lower limit voltage values which are given previously in conformity with the expected voltage value by a fixed value that corresponds to the special differential voltage value.
The seventeenth aspect of the present invention reside in that storage medium having the above sixteenth feature for having a testing program stored therein for testing a semiconductor integrated circuit, which enables execution of the testing method, which further comprises the steps of:
determining whether the special output voltage falls within the standard voltage range specified by the upper and lower standard voltage values;
regarding the semiconductor integrated circuit as a defective when the special output voltage falls out of the standard voltage range; and
regarding the semiconductor integrated circuit as a non-defective if the amplified deferential voltages fall within the determination voltage range while regarding the semiconductor integrated circuit as a defective if any of the amplified deferential voltages falls out of the determination voltage range, in the case where the special differential voltage falls within the standard voltage range.
The eighteenth aspect of the present invention resides in the storage medium having the above fourteenth feature for having a testing program stored therein for testing a semiconductor integrated circuit, which enables execution of a testing method wherein, even when the upper and lower limit values of the determination voltage range varies as the tonal level output from the terminals of the semiconductor integrated circuit is switched from one to another, the width of the determination voltage range is constant.
The nineteenth aspect of the present invention resides in the storage medium having the above fifteenth feature for having a testing program stored therein for testing a semiconductor integrated circuit, which enables execution of a testing method wherein, even when the upper and lower limit values of the determination voltage range varies as the tonal level output from the terminals of the semiconductor integrated circuit is switched from one to another, the width of the determination voltage range is constant.
The twentieth aspect of the present invention resides in the storage medium having the above sixteenth feature for having a testing program stored therein for testing a semiconductor integrated circuit, which enables execution of a testing method wherein, even when the upper and lower limit values of the determination voltage range varies as the tonal level output from the terminals of the semiconductor integrated circuit is switched from one to another, the width of the determination voltage range is constant.
The twenty-first aspect of the present invention resides in the storage medium having the above seventeenth feature for having a testing program stored therein for testing a semiconductor integrated circuit, which enables execution of a testing method wherein, even when the upper and lower limit values of the determination voltage range varies as the tonal level output from the terminals of the semiconductor integrated circuit is switched from one to another, the width of the determination voltage range is constant.
The twenty-second aspect of the present invention resides in the storage medium having the above seventeenth feature for having a testing program stored therein for testing a semiconductor integrated circuit, which enables execution of a testing method wherein the width of the determination voltage range is narrowed stepwise until the device under test is determined as a defective.
The twenty-third aspect of the present invention resides in the storage medium having the above twenty-secondth feature for having a testing program stored therein for testing a semiconductor integrated circuit, which enables execution of a testing method wherein semiconductor integrated circuits under test are classified into ranks, based on the variations of the output voltages in the determination voltage range when each device under test was determined as a defective.
According to the testing device and testing method for a semiconductor integrated circuit of the present invention, first, the voltage measuring means highly precisely measures the voltage values of plural tonal vantages output from a special D/A converter via the special output terminal corresponding thereto and computes the differential voltage value (digital value) between each measured voltage and the associated expected voltage. This differential voltage value is stored into the memory incorporated in the tester. The output voltages from the D/A converters via the output terminals other than the above special terminal are compared with the output voltage from the special D/A converter by the differential amplifiers. The comparison results, in other words, the amplified differential voltages from the differential amplifiers are supplied to the comparing and determining means (comparator). The comparator determines whether the amplified differential voltages from the differential amplifiers fall within a given voltage range (the determination voltage range). The upper and lower limit voltage values that specify the determination voltage range is set up by shifting the standard upper and lower limit voltage values, which have been set for the case where the tonal voltage output from the special output terminal is equal to the expected voltage, by a voltage value that corresponds to the above differential voltage value. Thus, the upper and lower limit voltages, based on which voltage comparison is to be made, can be modified in accordance with the deviation, of each tonal level voltage output from the special D/A converter, from the associated expected voltage. Therefore, it is possible to effect the test for each tonal level voltage correctly.
According to the testing device and testing method for semiconductor integrated circuits of the present invention, testing of a semiconductor integrated circuit such as a LCD driver LSI which has been developed to handle a greater number of outputs and a greater number of tones can be carried out by simultaneous judgements of all the amplified differential voltages in the comparator in combination with high-precision voltage measurement only on the output voltage from the special D/A converter via the special output terminal. Therefore, it is possible to markedly reduce the testing time as well as to sharply reduce the testing cost. Further, the differential amplification of the differential amplifiers (amplification of the differential voltage of each input from the special input by a predetermined amplification factor (e.g., 100 times, or greater)) promotes high precision in the comparing operation of the subsequent comparator, thus enabling highly precise testing.